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Not Applicable
The present invention relates in general to integrated circuits, and in particular to a versatile and efficient input termination method and circuitry with high impedance at power off.
Integrated circuits developed for applications such as data or telecommunication systems are often required to comply with standardized interface specifications and will vary depending on the standard. The transmission of information signals over transmission lines requires a termination impedance at the receiving side of the transmission line. Input termination circuits provide a termination impedance between input terminals. This termination impedance should match the characteristic impedance of the transmission line.
In the event of a power-failure at the receiving side of the transmission line, e.g., VDD=0V, the termination between the input terminals should go into a high-impedance mode so as not to load any driving circuitry connected to the input terminals.
FIG. 1 is a simplified high-level schematic diagram of a conventional input termination circuit 100. Incoming signals at terminals RTIP and RRING are differential signals that are ac coupled through a transformer (not shown) during normal operating conditions.
Generally, input termination circuit 100 provides a low-impedance termination between terminals RTIP and RRING during normal operating conditions and goes into a high-impedance mode during power-failure conditions. To operate properly, the voltages at terminals RTIP and RRING should remain sufficiently positive.
More specifically, a primary termination circuit 102 is coupled between terminals RTIP and RRING and includes a transistors M1 and resistors R1 and R2. A typical value for resistors R1 and R2 is 15 xcexa9. A control circuit 103 includes two transistors M2 and M3 and a resistor RG. A bias circuit 107 includes resistors R3 and R4, which provide a DC bias point of Vdd/2 at terminals RTIP and RRING. A typical value for resistors R3 and R4 is 10 Kxcexa9.
During normal operating conditions, e.g., VDD greater than 0V, a control signal CNTL controls the gate of transistor M1, via transistors M2 and M3. Control signal CNTL activates and deactivates primary termination circuit 102 by pulling the gate of transistor Ml high to VDD or low to ground, respectively. The control signal CNTL is generated from internal control logic.
During power-failure conditions, e.g., VDD=0V, transistors M2 and M3 turn off and resistor RG pulls the gate of transistor Ml to ground, turning it off. Thus, the termination between terminals RTIP and RRING goes into a high-impedance mode so as not to load any driving circuitry connected to terminals RTIP and RRING. During such power-failure conditions, the termination impedance seen between terminals RTIP and RRING is R3+R4. Transistor M1 stays off as long as the voltages at terminals RTIP and RRING are positive.
Input termination circuit 100 fails, however, if terminals RTIP and RRING become sufficiently negative to turn on transistor M1.
Thus, there is a need for an improved input termination circuit that operates under a variety of voltage levels at the input terminals.
The present invention provides a method and circuitry for an input termination. In accordance with the teachings of the invention, included is a primary termination circuit that provides a termination impedance between input terminals that turns off during power-failure conditions. The primary termination circuit puts the input termination circuit into a high-impedance mode. This prevents loading of any driving circuitry connected to terminals. A control circuit coupled to the primary termination circuit ensures that it stays off during power-failure conditions even when the voltage levels at the input terminals vary widely.
Accordingly, in one embodiment, the present invention includes a first transistor coupled between a first terminal and a second terminal. A control circuit monitors voltages on the first and second terminals and a first voltage source. During power off conditions, the control circuit couples the gate of the first transistor to a voltage that will keep the first transistor off.
Another embodiment includes a second transistor and a third transistor. During power off conditions, the second and third transistors couple the gate of the first transistor to the its acting source.
Another embodiment includes a control circuit that has a first circuit and a second circuit that can operate without power from the first voltage source. The first and second circuits can operate from power coming from the terminal having the higher voltage level.
In another embodiment, if there is a power off condition and if the first terminal voltage is a threshold greater than the second terminal voltage, the control circuit pulls the gate of the second transistor to the highest voltage potential and pulls the gate of the third transistor to the lowest voltage potential. Moreover, if there is a power off condition and if the second terminal voltage is a threshold greater than the third terminal voltage, the control circuit pulls the gate of the third transistor to the highest voltage potential and pulls the gate of the second transistor to the lowest voltage potential.
Embodiments of the present invention achieve their purposes and benefits in the context of known circuit and process technology and known techniques in the electronic and process arts. Further understanding, however, of the nature, features, and advantages of the present invention is realized by reference to the latter portions of the specification, accompanying drawings, and appended claims.